This invention relates generally to the design of digital integrated circuits, and more specifically to an improved edge-triggered scan flip-flop and one-pass scan synthesis method.
The use of integrated circuits is widespread and pervasive. Integrated circuits implement complex logic operations, and often do so through the use of an exceedingly large number of logic gates. A significant concern in the design and testing of integrated circuits is that the integrated circuit, often comprising well over one million logic gates, implements specified logic operations without error.
Ideally, every possible combination of inputs to an integrated circuit is applied when the integrated circuit is in every possible internal logic state, thus allowing every possible output of the circuit to be compared with the functional requirements of the circuit. However, even for a combinational circuit, which is a circuit in which the outputs of the circuit depend directly on the inputs to the circuit, and which thereby does not contain memory elements, the number of possible input combinations is sufficiently large that the test of the circuit becomes an NP hard problem, that is one that cannot be solved in polynomial time. For a sequential circuit, which is a circuit that contains internal memory and thus may have a number of internal logic states, the problem of testing every conceivable input combination in every combination of logic states of the circuit becomes even more intractable.
Further, testing of the circuit by manipulating the primary inputs and examining the primary outputs provides little information as to a location of a fault within the circuit. The knowledge that a certain combination of inputs to a circuit results in an incorrect combination of outputs from the circuit may be of little use in determining where in the circuit the error occurs.
One method known in the art of providing additional detail as to the internal operation of the circuit is to replace flip-flops normally found in the circuit with scan flip-flops. Generally speaking, almost any flip-flop present in a circuit may be converted to a scan flip-flop. Often a non-scan flip-flop is made scannable by adding a scan data input which is passed to a flip-flop output through the use of either a multiplexer and associated control signal or an independent clock. Such modifications increase circuit area and power requirements, and may otherwise affect circuit operation.
A scan flip-flop may be used as a control point for inserting a value into a circuit, or as an observation point for observing a value at a point in the circuit. Scan flip-flops are generally tied, or stitched, together to form a scan chain, with the scan chain forming a serial shift register. Data may be shifted in to provide input values for the circuit, or shifted out to capture the state of a portion of the circuit.
FIG. 1 illustrates a digital logic circuit. The digital logic circuit includes combinational circuit elements 11, 13. Scan flip-flops 15A-G are dispersed about the combinational circuit elements 11, 13. Each of the scan flip-flops 15A-G has four input ports for receiving associated input signals and one output port for outputting an associated output signal. The input ports are a data-in input port (DIN), a scan-in input port (SIN), a clock input port (CLK), and a test mode signal input port ({overscore (N)}/T). Each of the scan flip-flops has a single data-out output port (Q). The output Q is set to DIN after the rising edge of the clock signal when the test mode signal is set to a {overscore (TEST)} value. Thus, when the test mode signal is set to {overscore (TEST)} the scan flip-flop acts as an edge-triggered flip-flop. When the test mode signal is set to {overscore (TEST)}, however, the output signal Q is set to SIN after the rising edge of the clock signal. Thus, the scan flip-flops are edge-triggered flip-flops made scannable by adding a scan input and a multiplexer with an associated control signal.
In the digital logic circuit of FIG. 1, the combinational circuit 11 has at least four outputs 17A-D, each of which is passed to the DIN ports of the scan flip-flops 15A-D, respectively. The combinational circuit 13 has at least four inputs 19A-D, which are provided by the Q data output ports of the scan flip-flops 15A-D, respectively. The combinational circuit 13 also has at least three outputs 17E-G, which are connected to the DIN ports of the flip-flops 15E-G, respectively. All of the scan flip-flops 15A-G are provided a common clock CLK signal 21 and a common test mode {overscore (N)}/T signal 23.
The scan flip-flops 15A-G are formed into a serial scan chain, i.e., a serial shift register, by connecting the Q data output of one scan flip-flop to the SIN port of another scan flip-flop. Accordingly, in addition to connecting the Q data output 19A of scan flip-flop 15A to the combinational circuit 13, the Q data output 19A is also connected to the SIN scan input port of scan flip-flop 15B. Similarly, the Q data output 19B is connected to the SIN input port of scan flip-flop 15C, the Q data output 19C is connected to the SIN input port of scan flip-flop 15D, the Q data output 19D is connected to the SIN input port of scan flip-flop 15E, the Q data output 19E is connected to the SIN input port of scan flip-flop 15F, and the Q data output 19E is connected to the SIN input port of scan flip-flop 15G. In the circuit of FIG. 1, the SIN input 20 to scan flip-flop 15A is accessible by a circuit tester, and the Q data output 19G of scan flip-flop 15G is readable by the circuit tester. Accordingly, the scannable flip-flops 15A-G are stitched together to form a serial chain in the order of 15A-15B-15C-15D-15E-15F-15G.
The scan flip-flops act both as control points and observation points. Control points, of course, may be treated as pseudo-primary inputs (PIs) and observation points may be treated as pseudo-primary outputs (POs). By way of example, for the circuit of FIG. 1 the scan flip-flops 15A-G are first treated as pseudo-PIs and are provided an input test vector comprised of state bits. The input test vector is provided by setting the test mode signal to {overscore (TEST)} and sequentially placing input data on the SIN line 20 every clock cycle. The first clock cycle after the input data is placed on the SIN line shifts the input data to the SIN input of the next scan flip-flop in the scan chain. Accordingly, by sequentially placing data on the scan in line 20 on sequential clock cycles, each of the scan flip-flops in the scan chain may be loaded with a state bit from the test vector. Thereafter setting the test mode signal to {overscore (TEST)} allows for normal circuit operation, with the circuit utilizing the data input to the scan flip-flops as pseudo-primary outputs. After providing the circuit one or more (usually one) clock pulses to drive the system to an expected desired state the test mode signal is again set to {overscore (TEST)}. Thereafter providing clock signals to the circuit causes the data present on the output ports of the scan flip-flops to be sequentially shifted to the next scan flip-flop in the scan chain, with the data being read from output 19G by a tester.
Proper operation of the scan chain therefore generally requires that the scan shift chain operate in a race-free manner. If a race condition exists then the data in the scan chain may be corrupted and provide either an incorrect test vector or an incorrect indication of system state. For example, during a scan data shift operation an edge of the clock signal may reach scan flip-flop 15D a period of time prior to the edge of the clock signal reaching scan flip-flop 15E. If the period of time is sufficiently long, the input to the scan flip-flop 15D may be passed through the scan flip-flop 15D and propagated to the scan flip-flop 15E before the data previously at the input to scan flip-flop 15E is passed to the next scan flip-flop in the scan chain. The data previously at the input to scan flip-flop 15E would thereby be overwritten by the input to scan flip-flop 15D, with the result of either an incorrect test vector being loaded into the scan chain or an inaccurate reading of the system state being provided.
Furthermore, digital logic circuits are often designed using non-scan flip-flops which are later replaced, often automatically, with an equivalent scan flip-flop. The equivalent scan flip-flop is expected to substantially behave the same as the non-scan flip-flop it replaces, although this may not always be the case. This presents several problems. First, there may not be a one-to-one correspondence between non-scan flip-flops and scan flip-flops. That is, a single flip-flop may have different suitable scan equivalent flip-flops depending on the design constraints leading to the selection of any particular flip-flop. Second, the replacement of a non-scan flip-flop with a scan equivalent flip-flop may introduce variances from the timing, area and power constraints of a particular portion of a circuit. Additionally, the automatic replacement of non-scan flip-flops with scan flip-flops hides details of circuit operation from the circuit designer, increasing the difficulty of the design task. Finally, any replacement of a flip-flop chosen by the designer during initial design tasks, as well as later scan chain stitching may cause unexpected circuit timing, area, loading, or other impacts, creating a need for the designer to revisit the design late in the design cycle.
The present invention therefore provides a scan flip-flop and methodology which reduces the possibility, among other items, of race problems during scan shift operations and which provides circuit designers additional control over circuit design elements. According to the present invention a scan flip-flop is provided having a data-in signal input, a scan-in signal input, and a test signal input. A scan flip-flop also has a data-out signal output and a scan-out signal output, with a data-out driver and a scan-out signal driver forming these outputs. When a test mode signal is of a first value the scan-out signal and the data-out signal are coupled to the data-in signal. When the test mode signal is a second value the data-out signal and the scan-out signal are coupled to the scan-in signal. In one embodiment, the scan-out signal driver is a weak current source and is therefore a weak signal driver. In the same or in another embodiment, a circuit element, which may be a buffer, an inverter, or other simple logic gates, is inserted in the signal path prior to the scan-out signal driver to introduce delay in the scan-out signal path. In both cases, a substantially constant and predictable load is presented on the data-out signal path.
The scan flip-flop from the present invention may also comprise a multiplexer which sets a multiplexer output based on either a data input or a scan input depending on the value of a control input. The output of a multiplexer is coupled to a transfer gate having an input and an output, with a clock control signal setting the transfer gate output to the transfer gate input. A latch with an input and an output holds the gated transfer gate output. The value held by the latch is provided to a data-out signal driver having an input and an output, with the output providing the data output for the circuit. The output of the data-out signal driver is also provided to a scan-out signal driver having a small current drive capability.
The present invention also provides a process of designing digital logic circuits with race-free scan shift change using one-pass scan synthesis. In such a process a circuit designer designs digital logic circuits having flip-flops. The flip-flops are scan flip-flops having separate data outputs and scan outputs, with the load on the scan output not affecting drive characteristics of the data output signal.
A digital electronic circuit with scan flip-flops elements may therefore be designed by providing a high level language description representing the digital electronic circuit. A list of logic components and interconnections between the logic components is generated from the high level language description, the list of logic components including a plurality of flip-flop components. The logic components are mapped to cells, with each cell specifying a specific electronic circuit component. The flip-flop components are mapped to at least one scan flip-flop cell. The scan flip-flop cell has at least two inputs, a data input and a scan input, and at least two outputs, a data output and a scan output. Each of the data output and the scan output is driven by a signal driver, with the scan output signal driver being a weak signal driver. In another embodiment, a circuit delay element is placed in the scan-in signal path.
Many of the attendant features of this invention will be more readily appreciated as the same becomes better understood by reference to the following detailed description considered in connection with the accompanying drawings.